Optimal utilization of low voltage GaN HEMT in high frequency boost converter

In this paper, investigations on optimal topology and operation mode for low voltage GaN HEMT are performed. Analytical loss model of GaN HEMT, in which influences of circuit and package parasitics are accounted for, is developed as a tool to analyze losses in GaN HEMT in different switching conditions. Analysis results shows that when applied in both Vout <; 2Vin and Vout > 2Vin situations in Boundary Conduction Mode with Valley Switching(BCM-VS) in a boost converter, where GaN HEMT is switched on when voltage across it is lowered, switching loss can be greatly reduced. Switching loss reduction results not only from the exemption of discharging the large output capacitance of GaN HEMT at high voltage, but also from the fact that parasitic inductance has much less effects on switching loss in GaN HEMT in BCM-VS than in Continuous Conduction Mode (CCM). Limitations and design tradeoffs when GaN HEMT is applied in BCM-VS are also revealed. Forward voltage of GaN HEMT in reverse conduction is high and its conduction should be prevented when Vout > 2Vin to achieve conduction loss reduction. This further loss reduction can be realized by switching on transistor before valley point. Besides, in BCM-VS, overvoltage on GaN HEMT is larger and oscillatory energy dissipation in circuit is higher than in CCM due to higher turn off current. Paralleling external capacitor to the transistor helps to ease voltage stress; however turn on loss will be increased. This loss increase is more severe in the case of Vout <; 2Vin than Vout > 2Vin. Trade-offs on the selection of proper external capacitor value exists between increased switching loss and reduced voltage stress. Experimental setup is built to verify and demonstrate the analysis.