G. Caiulo, F. Maloberti, G. Palmisano, S. Portaluri
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引用次数: 0
摘要
讨论了一种适用于高频应用的CMOS功率缓冲器。使用高速推挽输出级和高度线性共模反馈，即使在非常高的输入频率下也能保持良好的线性度。事实上，在0.5 MHz和1 MHz下，总谐波失真(THD)分别达到66 dB和58 dB，负载电阻为75¿。此外，该电路提供了62 dB的直流增益和60 MHz的增益带宽积。该集成原型采用1.2 m CMOS工艺实现，占地280 mils2的硅面积。
A High Frequency CMOS Power Buffer with Extended Linearity
A CMOS power buffer suitable for high frequency applications is discussed. The use of a high-speed push-pull output stage and a highly-linear common mode feedback allow good linearity to be maintained even with very high input frequencies. Indeed, Total Harmonic Distortions (THD) as good as ¿66 dB and ¿58 dB are achieved at 0.5 MHz and 1 MHz, respectively, with a load resistance of 75 ¿. Moreover, the circuit provides a dc gain of 62 dB and a gain-bandwidth product of 60 MHz. The integrated prototype, realized using a 1.2 ¿m CMOS process, occupies a silicon area of 280 mils2.
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