{"title":"基于CMOS和GDI逻辑的32位CSLA的比较分析","authors":"G. T. Amizhdhu, P. Samundiswary","doi":"10.1109/ICEES.2018.8442407","DOIUrl":null,"url":null,"abstract":"Adders are the basic building blocks used in various computational units and processors. Carry Select Adder (CSLA) is one of the simple and fastest multi bit adders used in various high-speed processors. However, CSLA designed using CMOS logic suffers from design complexity, which leads to increase in power consumption and area. Hence in this paper., CSLA is designed using GDI logic. GDI is well suitable for designing low power circuits with reduced transistor count. In this paper, 32-bit CSLA is designed using CMOS and GDI logic and their performance parameters such as power, delay and transistor count are analyzed using HPSICE software. From simulation results, it is observed that the modified CSLA using BEC based on GDI logic achieves 69.36% and 66.92% reduction in power and transistor count respectively compared to that of CSLA based CMOS logic.","PeriodicalId":134828,"journal":{"name":"2018 4th International Conference on Electrical Energy Systems (ICEES)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Comparative analysis of 32-bit CSLA based on CMOS and GDI logic\",\"authors\":\"G. T. Amizhdhu, P. Samundiswary\",\"doi\":\"10.1109/ICEES.2018.8442407\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Adders are the basic building blocks used in various computational units and processors. Carry Select Adder (CSLA) is one of the simple and fastest multi bit adders used in various high-speed processors. However, CSLA designed using CMOS logic suffers from design complexity, which leads to increase in power consumption and area. Hence in this paper., CSLA is designed using GDI logic. GDI is well suitable for designing low power circuits with reduced transistor count. In this paper, 32-bit CSLA is designed using CMOS and GDI logic and their performance parameters such as power, delay and transistor count are analyzed using HPSICE software. From simulation results, it is observed that the modified CSLA using BEC based on GDI logic achieves 69.36% and 66.92% reduction in power and transistor count respectively compared to that of CSLA based CMOS logic.\",\"PeriodicalId\":134828,\"journal\":{\"name\":\"2018 4th International Conference on Electrical Energy Systems (ICEES)\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-02-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 4th International Conference on Electrical Energy Systems (ICEES)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICEES.2018.8442407\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 4th International Conference on Electrical Energy Systems (ICEES)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEES.2018.8442407","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Comparative analysis of 32-bit CSLA based on CMOS and GDI logic
Adders are the basic building blocks used in various computational units and processors. Carry Select Adder (CSLA) is one of the simple and fastest multi bit adders used in various high-speed processors. However, CSLA designed using CMOS logic suffers from design complexity, which leads to increase in power consumption and area. Hence in this paper., CSLA is designed using GDI logic. GDI is well suitable for designing low power circuits with reduced transistor count. In this paper, 32-bit CSLA is designed using CMOS and GDI logic and their performance parameters such as power, delay and transistor count are analyzed using HPSICE software. From simulation results, it is observed that the modified CSLA using BEC based on GDI logic achieves 69.36% and 66.92% reduction in power and transistor count respectively compared to that of CSLA based CMOS logic.