基于CMOS和GDI逻辑的32位CSLA的比较分析

G. T. Amizhdhu, P. Samundiswary
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引用次数: 0

摘要

加法器是各种计算单元和处理器中使用的基本构件。进位选择加法器(CSLA)是一种简单和最快的多比特加法器,用于各种高速处理器。然而,使用CMOS逻辑设计的CSLA存在设计复杂性,从而导致功耗和面积的增加。因此在本文中。CSLA采用GDI逻辑进行设计。GDI非常适合设计晶体管数量较少的低功耗电路。本文采用CMOS和GDI逻辑设计了32位CSLA,并利用HPSICE软件对其功耗、延迟和晶体管数等性能参数进行了分析。仿真结果表明,与基于CMOS逻辑的CSLA相比,基于GDI逻辑的BEC改进CSLA的功耗和晶体管数量分别降低了69.36%和66.92%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Comparative analysis of 32-bit CSLA based on CMOS and GDI logic
Adders are the basic building blocks used in various computational units and processors. Carry Select Adder (CSLA) is one of the simple and fastest multi bit adders used in various high-speed processors. However, CSLA designed using CMOS logic suffers from design complexity, which leads to increase in power consumption and area. Hence in this paper., CSLA is designed using GDI logic. GDI is well suitable for designing low power circuits with reduced transistor count. In this paper, 32-bit CSLA is designed using CMOS and GDI logic and their performance parameters such as power, delay and transistor count are analyzed using HPSICE software. From simulation results, it is observed that the modified CSLA using BEC based on GDI logic achieves 69.36% and 66.92% reduction in power and transistor count respectively compared to that of CSLA based CMOS logic.
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