内存测试地址生成的改进灰色序列和计数器序列

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Pub Date : 2006-06-22 DOI:10.1109/MIXDES.2006.1706645

S. Yarmolik, V. Yarmolik

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引用次数: 17

摘要

本文的目的是提出一种新的用于模式敏感故障检测的内存测试地址生成技术。已经证明，先前基于多次运行内存测试的结果仅对第一次迭代非常有效。为了实现高故障覆盖率，必须使用不同类型的修改。提出了两种存储器地址变换方法，并对其进行了分析和实验验证

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Modified Gray And Counter Sequences For Memory Test Address Generation

The goal of this paper is to propose the new techniques for memory test address generation for pattern sensitive faults detection. It has been shown that the previous results based on the multiple runs memory testing are very efficient only for the first iterations. To achieve the high fault coverage the different types of modification have to be used. Two kind of memory address transformation have been proposed, analysed and experimentally validated

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Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.

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