{"title":"一种适用于低电压低功率信号处理的新型高性能有源模块","authors":"Atul Kumar, B. Chaturvedi, Shafali Jagga","doi":"10.1145/3549206.3549320","DOIUrl":null,"url":null,"abstract":"Abstract: In this research paper, a novel low-voltage low-power current follower differential input transconductance amplifier (CFDITA) based on floating gate MOS is presented. The proposed CFDITA has an important feature of electronic controllability with the help of bias current. Moreover, this design is realized with both PMOS and NMOS current mirror structures using floating gate technique. So, another important feature of the design is that it operates in bilateral mode. It is designed at a supply voltage of ± 0.75V and consumes a power of 0.8 mW at 100 μA bias current. All the results provided to verify the device performance are simulated using SPICE with 0.18 μm CMOS technology process parameters. The simulation results confirm the theoretical concepts.","PeriodicalId":199675,"journal":{"name":"Proceedings of the 2022 Fourteenth International Conference on Contemporary Computing","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A New High Performance Active Building Block Suitable for Low Voltage Low Power Signal Processing\",\"authors\":\"Atul Kumar, B. Chaturvedi, Shafali Jagga\",\"doi\":\"10.1145/3549206.3549320\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Abstract: In this research paper, a novel low-voltage low-power current follower differential input transconductance amplifier (CFDITA) based on floating gate MOS is presented. The proposed CFDITA has an important feature of electronic controllability with the help of bias current. Moreover, this design is realized with both PMOS and NMOS current mirror structures using floating gate technique. So, another important feature of the design is that it operates in bilateral mode. It is designed at a supply voltage of ± 0.75V and consumes a power of 0.8 mW at 100 μA bias current. All the results provided to verify the device performance are simulated using SPICE with 0.18 μm CMOS technology process parameters. The simulation results confirm the theoretical concepts.\",\"PeriodicalId\":199675,\"journal\":{\"name\":\"Proceedings of the 2022 Fourteenth International Conference on Contemporary Computing\",\"volume\":\"41 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-08-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 2022 Fourteenth International Conference on Contemporary Computing\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/3549206.3549320\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2022 Fourteenth International Conference on Contemporary Computing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/3549206.3549320","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A New High Performance Active Building Block Suitable for Low Voltage Low Power Signal Processing
Abstract: In this research paper, a novel low-voltage low-power current follower differential input transconductance amplifier (CFDITA) based on floating gate MOS is presented. The proposed CFDITA has an important feature of electronic controllability with the help of bias current. Moreover, this design is realized with both PMOS and NMOS current mirror structures using floating gate technique. So, another important feature of the design is that it operates in bilateral mode. It is designed at a supply voltage of ± 0.75V and consumes a power of 0.8 mW at 100 μA bias current. All the results provided to verify the device performance are simulated using SPICE with 0.18 μm CMOS technology process parameters. The simulation results confirm the theoretical concepts.