{"title":"50ns / 15v可变n通道非易失性存储器器件","authors":"M. Horiuchi, H. Katto","doi":"10.1109/IEDM.1980.189903","DOIUrl":null,"url":null,"abstract":"A new structure for a Floating Si-gate Channel Corner Avalanche Transition nonvolatile memory device (FCAT-II) is described. The new structure uses a modification of the previously reported FCAT (FCAT-I). The key improvement is that the floating gate couples better with the control gate. This device can oprate in both write and erase modes under high speed ( ≥ 50 ns( and low voltage ( ≤ 15 V) condition. Another useful feature is the saturation of the high level thresold voltage independent of write pulse widhs greater than 50 ns.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"9 1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 50 ns/15 V alterable n-channel nonvolatile memory device\",\"authors\":\"M. Horiuchi, H. Katto\",\"doi\":\"10.1109/IEDM.1980.189903\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new structure for a Floating Si-gate Channel Corner Avalanche Transition nonvolatile memory device (FCAT-II) is described. The new structure uses a modification of the previously reported FCAT (FCAT-I). The key improvement is that the floating gate couples better with the control gate. This device can oprate in both write and erase modes under high speed ( ≥ 50 ns( and low voltage ( ≤ 15 V) condition. Another useful feature is the saturation of the high level thresold voltage independent of write pulse widhs greater than 50 ns.\",\"PeriodicalId\":180541,\"journal\":{\"name\":\"1980 International Electron Devices Meeting\",\"volume\":\"9 1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1980 International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.1980.189903\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1980 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1980.189903","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 50 ns/15 V alterable n-channel nonvolatile memory device
A new structure for a Floating Si-gate Channel Corner Avalanche Transition nonvolatile memory device (FCAT-II) is described. The new structure uses a modification of the previously reported FCAT (FCAT-I). The key improvement is that the floating gate couples better with the control gate. This device can oprate in both write and erase modes under high speed ( ≥ 50 ns( and low voltage ( ≤ 15 V) condition. Another useful feature is the saturation of the high level thresold voltage independent of write pulse widhs greater than 50 ns.
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