S. Krishnan, E. M. Sankara Narayanan, Y.Z. Xu, F. Clough, M. M. De Souza, D. Flores, M. Vellvehí, J. Millán
{"title":"新型可变掺杂槽双栅高压TFT","authors":"S. Krishnan, E. M. Sankara Narayanan, Y.Z. Xu, F. Clough, M. M. De Souza, D. Flores, M. Vellvehí, J. Millán","doi":"10.1109/MIEL.2002.1003163","DOIUrl":null,"url":null,"abstract":"A novel high performance dual gated, glass compatible polycrystalline silicon HVTFT with blocking voltage in excess of 300 V is demonstrated. This device shows an order of magnitude improvement in the on-state performance in comparison to its offset drain (DG-OD) counterpart. The significantly enhanced performance of this dual gate device is due to an offset region doped through slots of reducing dimensions from the source (control gate) to the drain (sub-gate).","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Novel dual gate high voltage TFT with variable doping slot\",\"authors\":\"S. Krishnan, E. M. Sankara Narayanan, Y.Z. Xu, F. Clough, M. M. De Souza, D. Flores, M. Vellvehí, J. Millán\",\"doi\":\"10.1109/MIEL.2002.1003163\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel high performance dual gated, glass compatible polycrystalline silicon HVTFT with blocking voltage in excess of 300 V is demonstrated. This device shows an order of magnitude improvement in the on-state performance in comparison to its offset drain (DG-OD) counterpart. The significantly enhanced performance of this dual gate device is due to an offset region doped through slots of reducing dimensions from the source (control gate) to the drain (sub-gate).\",\"PeriodicalId\":221518,\"journal\":{\"name\":\"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MIEL.2002.1003163\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MIEL.2002.1003163","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Novel dual gate high voltage TFT with variable doping slot
A novel high performance dual gated, glass compatible polycrystalline silicon HVTFT with blocking voltage in excess of 300 V is demonstrated. This device shows an order of magnitude improvement in the on-state performance in comparison to its offset drain (DG-OD) counterpart. The significantly enhanced performance of this dual gate device is due to an offset region doped through slots of reducing dimensions from the source (control gate) to the drain (sub-gate).