采用动态相对延迟的低功耗片上总线架构

IEEE International SOC Conference, 2004. Proceedings. Pub Date : 2004-11-30 DOI:10.1109/SOCC.2004.1362419

M. Ghoneima, Y. Ismail

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引用次数: 1

摘要

提出了一种用于低功耗片上总线的动态延迟总线方案。该方案在具有一定交换活动的母线上动态引入延迟，使相对交换相邻线路之间产生相对延迟。该方案所引入的最佳相对延迟可使功耗降低16%。

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Low-power on-chip bus architecture using dynamic relative delays

This paper proposes a dynamic delayed line bus scheme (DDL) for low-power on-chip buses. This scheme dynamically introduces a delay to bus lines having a certain switching activity to create relative delay between opposite switching adjacent lines. The optimum relative delay introduced by this proposed scheme is shown to reduce the power dissipation by up to 16%.

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来源期刊

IEEE International SOC Conference, 2004. Proceedings.

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