Z1 AND Z2 Kerf Delta: A Key Blade Parameter for Top Chipping Control

Silicon wafers are becoming thinner with layers of metallization of different chemistries and material properties added on the saw lane and at the backside of the wafer. Such structures are imposing novel challenges to sawing process application. To satisfy the separation requirements of both material layers on top and backside, wafer dicing employs step cut process to control the induced stress by proportional sharing of loads between the two individual blades, namely, ZI(bladel) and Z2(blade2). The cut width or kerf of the second blade (Z2) should be relatively narrower than Z1 's kerf to avoid double cutting characterized by the condition when Z2 is touching the kerf's wall made by Z1. The difference in kerfs width of these two blades is called kerf delta AMP defect Pareto showed that the top chip on silicon dice has always been in the top 3 defects in Wafer Saw Process. The monthly reject rate showed this defect is posting high reject contribution to the defined business target for year 2021 operation. By structural problem-solving approach, root causes were identified. The primary corrective action of increasing the blade's kerf delta to 1.55: 1 (Z1:Z2 thickness ratio) in combination with the optimized settings, of 50/50 (%Z1/%Z2 cut depth), top chipping defects had significantly reduced and managed within the target rejection rate.