Silicon validation of evolution-designed circuits

No silicon fabrication and characterization of circuits with topologies designed by evolution has been done before, leaving open questions about the feasibility of the evolutionary design approach, as well as on how high performance, robust, or portable such designs could really be when implemented in hardware. This paper is the first to report on a silicon implementation of circuits evolved in simulation. Several circuits were evolved and fabricated in a 0.5-micron CMOS process. This paper focuses on results of logical gates evolved at a transistor level. It discusses the steps taken in order to increase the chances of robust and portable designs, summarizes the results of characterization tests based on chip measurements, and comments on the performance comparing to simulations.