Design and Implementation of a High-Speed D Flip Flop using CMOS Inverter Logic

This paper proposes an improvised D- flip flop configuration based on tristate inverter logic, which reduces the power dissipation, decrease the transition time from the input to output as well as reduced time to reach rail to rail voltage. The flip flop uses transmission gate instead of pass transistor to achieve this requirement. The design is simulated using 90nm CMOS technology and data is propagated at 50% duty cycle. The circuit is simulated using Cadence tools to assess the performance with respect to delay and power. These D-flip flops have numerous applications such as buffers, registers, digital VLSI clocking systems, microprocessors etc.