An FPGA-based incremental encoder signal conditioner with reduced error in rotational rate estimation over a wide range of rotational speeds

Digital motion controllers (DMC) usually employ incremental encoders (IE) as angular position sensors and deploy one out of a handful of candidate algorithms to estimate the rotational rate from the pulse counts obtained from the IE at a periodic rate. The electronics for signal conditioning of the IE output pulse trains, elimination of input glitches and pulse multiplier for resolution enhancement are well-established hardware and all state-of-the-art DMCs have on-chip module of the same. The rate estimation algorithms based on the encoder pulse counts, however, tend to become erroneous at low rotational speeds. This problem is usually circumvented by a reciprocal counting mechanism, where the time between two successive IE pulses is measured to estimate the rotational rate. This paper proposes a seamless switching protocol between the two rate computing methods and presents the design of an Incremental Encoder Signal Conditioner (IESC) and its FPGA-based implementation that embeds the direct and reciprocal rate computation algorithms along with the automated changeover mechanism between the two for a more accurate estimation of rotational speed in a wide range of rotational speeds. The paper also presents the performance of the IESC over a large range of rotational rates.