A DRAM compiler for fully optimized memory instances

System-on-Chip (SoC) designs will soon be dominated by on-chip memory so there is an urgent need for customization of memory semiconductor intellectual property (SIP) to increase product differentiation. This paper describes a software compiler tool which can be used to customize DRAM memory arrays in both pure logic and merged logic processes. This compiler optimizes memory macrocells for speed, power, and area to obtain radically reduced area and power when compared to SRAM implementations. It can also create custom memories with very fine granularity.