{"title":"试验计划的组合方案(以微处理器系统为例)","authors":"Mark Sh. Levin, Alexey O. Merzlyakov","doi":"10.1109/SIBIRCON.2008.4602579","DOIUrl":null,"url":null,"abstract":"This paper focuses on designing an efficient test strategy (plan) for a set of microprocessor systems. The problem is examined as a composite one. A four-stage solving scheme is suggested. The following underlying models are used: (i) multicriteria ranking, (ii) knapsack-like problems (e.g., multicriteria multiple choice problem), (iii) clustering, and (iv) multicriteria assignment/allocation.","PeriodicalId":295946,"journal":{"name":"2008 IEEE Region 8 International Conference on Computational Technologies in Electrical and Electronics Engineering","volume":"115 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Composite combinatorial scheme of test planning (example for microprocessor systems)\",\"authors\":\"Mark Sh. Levin, Alexey O. Merzlyakov\",\"doi\":\"10.1109/SIBIRCON.2008.4602579\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper focuses on designing an efficient test strategy (plan) for a set of microprocessor systems. The problem is examined as a composite one. A four-stage solving scheme is suggested. The following underlying models are used: (i) multicriteria ranking, (ii) knapsack-like problems (e.g., multicriteria multiple choice problem), (iii) clustering, and (iv) multicriteria assignment/allocation.\",\"PeriodicalId\":295946,\"journal\":{\"name\":\"2008 IEEE Region 8 International Conference on Computational Technologies in Electrical and Electronics Engineering\",\"volume\":\"115 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-07-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE Region 8 International Conference on Computational Technologies in Electrical and Electronics Engineering\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SIBIRCON.2008.4602579\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE Region 8 International Conference on Computational Technologies in Electrical and Electronics Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIBIRCON.2008.4602579","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Composite combinatorial scheme of test planning (example for microprocessor systems)
This paper focuses on designing an efficient test strategy (plan) for a set of microprocessor systems. The problem is examined as a composite one. A four-stage solving scheme is suggested. The following underlying models are used: (i) multicriteria ranking, (ii) knapsack-like problems (e.g., multicriteria multiple choice problem), (iii) clustering, and (iv) multicriteria assignment/allocation.