数字预失真子系统中一种高效的环路延迟估计器

Shitao Zhu, A. Zhang, Zhuo Xu, Xiaoli Dong
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引用次数: 3

摘要

提出了一种高效的时延估计方法,以获得数字预失真子系统中输入信号与时滞反馈信号在同一过程中的精确环路时延(包括整数和分数环时延)。与传统的复杂信号采样位置调整方案相比,利用分段抛物滤波辅助有限数据长度的稳定决策准则,显著降低了时间复杂度,提高了环路延迟估计的稳定性和精度。仿真和实验结果表明,该方法是高效有效的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A high-efficiency loop delay estimator in digital predistortion subsystem
A high-efficiency time delay estimation method is presented to obtain the accurate loop delay (including integer and fractional loop delay) between the input signal and the time delayed feedback signal in digital predistortion subsystem within the same process. Compared with the conventional, a sampling position adjusting scheme for complex signals using the piecewise-parabolic filter assisted by a steady decision criterion for limited data length achieves a significant reduction in time complexity and an improvement in loop delay estimation stability and precision. Results from simulations and experiments show that the proposed method is high-efficiency and valid.
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