{"title":"后处理局部电子注入非对称通栅晶体管改善40nm 6T-SRAM静态噪声余量的分析","authors":"K. Miyaji, D. Kobayashi, K. Takeuchi, S. Miyano","doi":"10.1109/IRPS.2013.6531982","DOIUrl":null,"url":null,"abstract":"Improvement of the static noise margin (SNM) in 40nm 6T-SRAM with local electron injected asymmetric pass gate (PG) transistor is analyzed. Lower word-line voltage during injection shows higher PG VTH shift and SNM improvement. SNM variation decreases by 13.6% after injection using pseudo disturb. Pull up transistor |VTH| decrease degrades write margin. Under voltage and thermal retention stress, average SNM improvement of the worst 10 cells out of 1k cells decreases by 7.0% at 3.4×105s.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Analysis on static noise margin improvement in 40nm 6T-SRAM with post-process local electron injected asymmetric pass gate transistor\",\"authors\":\"K. Miyaji, D. Kobayashi, K. Takeuchi, S. Miyano\",\"doi\":\"10.1109/IRPS.2013.6531982\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Improvement of the static noise margin (SNM) in 40nm 6T-SRAM with local electron injected asymmetric pass gate (PG) transistor is analyzed. Lower word-line voltage during injection shows higher PG VTH shift and SNM improvement. SNM variation decreases by 13.6% after injection using pseudo disturb. Pull up transistor |VTH| decrease degrades write margin. Under voltage and thermal retention stress, average SNM improvement of the worst 10 cells out of 1k cells decreases by 7.0% at 3.4×105s.\",\"PeriodicalId\":138206,\"journal\":{\"name\":\"2013 IEEE International Reliability Physics Symposium (IRPS)\",\"volume\":\"4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-04-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE International Reliability Physics Symposium (IRPS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IRPS.2013.6531982\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE International Reliability Physics Symposium (IRPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IRPS.2013.6531982","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Analysis on static noise margin improvement in 40nm 6T-SRAM with post-process local electron injected asymmetric pass gate transistor
Improvement of the static noise margin (SNM) in 40nm 6T-SRAM with local electron injected asymmetric pass gate (PG) transistor is analyzed. Lower word-line voltage during injection shows higher PG VTH shift and SNM improvement. SNM variation decreases by 13.6% after injection using pseudo disturb. Pull up transistor |VTH| decrease degrades write margin. Under voltage and thermal retention stress, average SNM improvement of the worst 10 cells out of 1k cells decreases by 7.0% at 3.4×105s.
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