{"title":"DSP设计采用VLIW架构","authors":"L. Lee, B.S. Suparjo, R. Wagiran, R. Sidek","doi":"10.1109/SMELEC.2000.932456","DOIUrl":null,"url":null,"abstract":"Programmable digital signal processors (pDSPs) are microprocessors that are specialized to perform well in digital signal processing intensive applications. A standard microprocessor can do most pDSP operations. However, the pDSP chip has better ability to perform number crunching algorithms in real-time, and pDSPs are highly flexible because they can be reprogrammed. The major objective of this research is to design and implement a general-purpose programmable DSP core (digital signal processor core). The architecture of the pDSP core must be designed in such a way that parallel processing can be exploited and computational units can be integrated into the core with ease. The pDSP designed is a fixed-point DSP based on a very long instruction word (VLIW) architecture. One way to overcome the performance limitation is to use field programmable gate array (FPGA) technology, a technology which gives the designer a higher degree of parallelism and ease of pDSP design.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"192 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"DSP design using VLIW architecture\",\"authors\":\"L. Lee, B.S. Suparjo, R. Wagiran, R. Sidek\",\"doi\":\"10.1109/SMELEC.2000.932456\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Programmable digital signal processors (pDSPs) are microprocessors that are specialized to perform well in digital signal processing intensive applications. A standard microprocessor can do most pDSP operations. However, the pDSP chip has better ability to perform number crunching algorithms in real-time, and pDSPs are highly flexible because they can be reprogrammed. The major objective of this research is to design and implement a general-purpose programmable DSP core (digital signal processor core). The architecture of the pDSP core must be designed in such a way that parallel processing can be exploited and computational units can be integrated into the core with ease. The pDSP designed is a fixed-point DSP based on a very long instruction word (VLIW) architecture. One way to overcome the performance limitation is to use field programmable gate array (FPGA) technology, a technology which gives the designer a higher degree of parallelism and ease of pDSP design.\",\"PeriodicalId\":359114,\"journal\":{\"name\":\"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)\",\"volume\":\"192 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-11-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SMELEC.2000.932456\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMELEC.2000.932456","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Programmable digital signal processors (pDSPs) are microprocessors that are specialized to perform well in digital signal processing intensive applications. A standard microprocessor can do most pDSP operations. However, the pDSP chip has better ability to perform number crunching algorithms in real-time, and pDSPs are highly flexible because they can be reprogrammed. The major objective of this research is to design and implement a general-purpose programmable DSP core (digital signal processor core). The architecture of the pDSP core must be designed in such a way that parallel processing can be exploited and computational units can be integrated into the core with ease. The pDSP designed is a fixed-point DSP based on a very long instruction word (VLIW) architecture. One way to overcome the performance limitation is to use field programmable gate array (FPGA) technology, a technology which gives the designer a higher degree of parallelism and ease of pDSP design.