Y. Chou, L. Callejo, M. Biedenbander, K. Lee, B. Allen, R. Lai, Q. Kan, R. Grundbacher, D. Leung, D. Eng, T. Block, A. Oki
{"title":"高温寿命试验对GaAs PHEMT双栅mmic低频噪声性能的影响[LNA示例]","authors":"Y. Chou, L. Callejo, M. Biedenbander, K. Lee, B. Allen, R. Lai, Q. Kan, R. Grundbacher, D. Leung, D. Eng, T. Block, A. Oki","doi":"10.1109/ROCS.2004.184348","DOIUrl":null,"url":null,"abstract":"The dual gate layout configuration has become a versatile approach for compact and high performance MMIC design for commercial, and military/space applications. In this paper, we describe a method that was developed to lifetest compact (0.81 mm/sup 2/) dual gate GaAs PHEMT low noise amplifiers (LNAs) operating from DC to 1 GHz. The objective of the lifetest is to evaluate the effect of elevated temperature on low frequency noise performance from 10-40 MHz. The results exhibit a decrease of noise figure (NF) at 10-40 MHz (approximately 0.25 to 0.5 dB) in a dual gate LNA subjected to lifetest at T/sub ambient/ of 200/spl deg/C. This might be attributed to the gate leakage current reduction at either the interface of gate metal-AlGaAs or nitride-AlGaAs, thus possibly reducing the effect of generation-recombination (primary origin of low frequency noise). On the other hand, the change of noise figure at frequencies beyond 100 MHz is not noticeable. In summary, we have demonstrated a method to effectively lifetest a compact and high performance MMIC designed with a dual gate configuration.","PeriodicalId":437858,"journal":{"name":"JEDEC (formerly the GaAs REL Workshop) ROCS Workshop, 2004.","volume":"78 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"The effect of elevated temperature lifetest on low frequency noise performance in GaAs PHEMT dual gate MMICs [LNA example]\",\"authors\":\"Y. Chou, L. Callejo, M. Biedenbander, K. Lee, B. Allen, R. Lai, Q. Kan, R. Grundbacher, D. Leung, D. Eng, T. Block, A. Oki\",\"doi\":\"10.1109/ROCS.2004.184348\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The dual gate layout configuration has become a versatile approach for compact and high performance MMIC design for commercial, and military/space applications. In this paper, we describe a method that was developed to lifetest compact (0.81 mm/sup 2/) dual gate GaAs PHEMT low noise amplifiers (LNAs) operating from DC to 1 GHz. The objective of the lifetest is to evaluate the effect of elevated temperature on low frequency noise performance from 10-40 MHz. The results exhibit a decrease of noise figure (NF) at 10-40 MHz (approximately 0.25 to 0.5 dB) in a dual gate LNA subjected to lifetest at T/sub ambient/ of 200/spl deg/C. This might be attributed to the gate leakage current reduction at either the interface of gate metal-AlGaAs or nitride-AlGaAs, thus possibly reducing the effect of generation-recombination (primary origin of low frequency noise). On the other hand, the change of noise figure at frequencies beyond 100 MHz is not noticeable. In summary, we have demonstrated a method to effectively lifetest a compact and high performance MMIC designed with a dual gate configuration.\",\"PeriodicalId\":437858,\"journal\":{\"name\":\"JEDEC (formerly the GaAs REL Workshop) ROCS Workshop, 2004.\",\"volume\":\"78 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"JEDEC (formerly the GaAs REL Workshop) ROCS Workshop, 2004.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ROCS.2004.184348\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"JEDEC (formerly the GaAs REL Workshop) ROCS Workshop, 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ROCS.2004.184348","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The effect of elevated temperature lifetest on low frequency noise performance in GaAs PHEMT dual gate MMICs [LNA example]
The dual gate layout configuration has become a versatile approach for compact and high performance MMIC design for commercial, and military/space applications. In this paper, we describe a method that was developed to lifetest compact (0.81 mm/sup 2/) dual gate GaAs PHEMT low noise amplifiers (LNAs) operating from DC to 1 GHz. The objective of the lifetest is to evaluate the effect of elevated temperature on low frequency noise performance from 10-40 MHz. The results exhibit a decrease of noise figure (NF) at 10-40 MHz (approximately 0.25 to 0.5 dB) in a dual gate LNA subjected to lifetest at T/sub ambient/ of 200/spl deg/C. This might be attributed to the gate leakage current reduction at either the interface of gate metal-AlGaAs or nitride-AlGaAs, thus possibly reducing the effect of generation-recombination (primary origin of low frequency noise). On the other hand, the change of noise figure at frequencies beyond 100 MHz is not noticeable. In summary, we have demonstrated a method to effectively lifetest a compact and high performance MMIC designed with a dual gate configuration.