90nm节点CMOS LOGIC生产中低能量掺杂和尖峰退火的USJ工艺要求

H. Nakao, Y. Momiyama, M. Kase, H. Ito, Y. Matsunaga
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引用次数: 0

摘要

ITRS路线图要求的源漏扩展(SDE)的超浅结(USJ)在超过90 nm节点的情况下向10 nm以下变浅。采用重质量掺杂的锑首次证明了n-MOS的45 nm节点USJ。在p-MOS的情况下,通过检查差分模式植入中器件性能的预加速能量依赖,我们发现对于超过90 nm节点的高端n-MOS来说,需要低电流的深亚kev能量污染植入。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
USJ process requirements on low energy doping and spike anneal for production for 90 nm node CMOS LOGIC
Ultra Shallow Junction (USJ) for Source Drain Extension (SDE) required from ITRS road map becomes shallower toward sub 10 nm beyond 90-nm node. The 45 nm node USJ for n-MOS was first demonstrated using heavy mass dopant of Antimony. In p-MOS case, by examining the pre-acceleration energy dependence of device performance in differential mode implant, we showed deep sub-keV energy contamination less high current implanter is necessary for high-end n-MOS beyond 90-nm node.
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