RTL implementation for a specific ALU of the 32-bit VLIW DSP processor core

Digital Signal Processors (DSPs) have shown the great strengths in digital signal processing algorithms such as digital filtering and Fourier analysis. This work is about an implementation for a specific computational unit based on the proposed RISC instruction set architecture (ISA) of 32-bit VLIW Fixed-point DSP processor core presented in our previous work. The computational unit is designed to be flexible for 32-bit/16-bit/8-bit data computations. The implementation is described from top-level to gate-level design and then it is verified to function correctly not only in Modelsim software but also on Altera Cyclone II (2C35) FPGA board.