加法器合并DRAM架构

Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) Pub Date : 2002-07-10 DOI:10.1109/MTDT.2002.1029768

M. Hashimoto

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引用次数: 0

摘要

提出了一种基于4进制加减运算可执行DRAM阵列的4级传感方案。实现该电路不会牺牲DRAM的功能、性能和硅面积。加法/减法将使用大规模并行SIMD执行，从而产生高度的并发性。将加法器实现在64 Mb的DRAM阵列中，可以达到50GOPS左右的性能。

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Adder merged DRAM architecture

A 4-level sensing scheme utilizing base-4 operation addition and subtraction executable DRAM array has been developed. Neither DRAM functions, performance, nor silicon area will be sacrificed by implementing the circuit. Addition/subtraction will be executed using the massively parallel SIMD, resulting in a high degree of concurrency. Performance of around 50GOPS performance can be achieved in the case where the adder is implemented into 64 Mb DRAM array.

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Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)

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