G.G. Lee, K. Fujihara, S. Kim, C. Oh, U. Chung, S.T. Ahn, M.Y. Lee
{"title":"一种智能批处理类型的RTA技术，用于256 Mbit以上的DRAM","authors":"G.G. Lee, K. Fujihara, S. Kim, C. Oh, U. Chung, S.T. Ahn, M.Y. Lee","doi":"10.1109/VLSIT.1995.520875","DOIUrl":null,"url":null,"abstract":"A new hot wall type rapid thermal annealing (H-RTA) technology using a vertical batch furnace has been developed. This technology provides junctions with shallow and high concentration and slip free process with high throughput. We have demonstrated that H-RTA is a promising candidate for device fabrications beyond 256 Mbit DRAM in cost as well as in performance.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A smart batch type RTA technology for beyond 256 Mbit DRAM\",\"authors\":\"G.G. Lee, K. Fujihara, S. Kim, C. Oh, U. Chung, S.T. Ahn, M.Y. Lee\",\"doi\":\"10.1109/VLSIT.1995.520875\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new hot wall type rapid thermal annealing (H-RTA) technology using a vertical batch furnace has been developed. This technology provides junctions with shallow and high concentration and slip free process with high throughput. We have demonstrated that H-RTA is a promising candidate for device fabrications beyond 256 Mbit DRAM in cost as well as in performance.\",\"PeriodicalId\":328379,\"journal\":{\"name\":\"1995 Symposium on VLSI Technology. Digest of Technical Papers\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-06-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1995 Symposium on VLSI Technology. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1995.520875\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1995 Symposium on VLSI Technology. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1995.520875","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A smart batch type RTA technology for beyond 256 Mbit DRAM
A new hot wall type rapid thermal annealing (H-RTA) technology using a vertical batch furnace has been developed. This technology provides junctions with shallow and high concentration and slip free process with high throughput. We have demonstrated that H-RTA is a promising candidate for device fabrications beyond 256 Mbit DRAM in cost as well as in performance.
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