基于等级的动态电压和频率缩放平铺图形处理器

B. Silpa, G. Krishnaiah, P. Panda
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引用次数: 11

摘要

随着对移动系统中复杂图形功能的兴趣日益增加,除了传统的性能增强标准之外,图形硬件的能耗正在成为主要的设计关注点。我们对各种现代游戏的研究证实,游戏的工作量会随着时间的变化而发生显著变化,因此可以从动态电压和频率缩放(DVFS)中获益。由于图形应用程序的视觉质量高度依赖于帧的处理速率,因此设计一个DVFS方案以最大限度地减少由于工作负载预测不准确而导致的截止日期错过是很重要的。在本文中,我们证明了平铺图形渲染器在获取帧参数方面比即时模式渲染器表现出实质性的优势,这些参数有助于提高工作负载估计的准确性。我们还表明,与“框架”相反,以更细粒度的“块”操作可以在错误预测的情况下早期发现和纠正行动。我们提出了一种准确的工作负载估计技术和两种DVFS方案:(i)基于瓦片历史的DVFS和(ii)基于瓦片等级的DVFS,用于瓦片渲染架构。所提出的方案被证明在功率和性能方面比最近文献中提出的帧级DVFS方案更有效。对于具有8个DVFS级别的系统,我们基于tile-history的DVFS方案比基于帧历史的DVFS方案在质量(截止日期错过)方面提高了60%,并节省了58%的能源。更复杂的基于瓦片等级的方案比基于框架历史的DVFS方案的质量提高了75%,并节省了58%的能源。我们还比较了所提出的瓦片级DVFS方案与帧级DVFS方案在不同数量的DVFS级别下的效率,发现虽然随着频率级别的增加,帧级方案的截止日期错过次数增加,但对瓦片级方案的影响可以忽略不计。我们方案的每帧能量率是最小的,表明它提供了最好的性能-能量结果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Rank based dynamic voltage and frequency scaling for tiled graphics processors
With increasing interest in sophisticated graphics capabilities in mobile systems, energy consumption of graphics hardware is becoming a major design concern in addition to the traditional performance enhancement criteria. Our study of various modern games substantiates the observation that the workload of games varies significantly with time and hence can benefit from dynamic voltage and frequency scaling (DVFS). Since visual quality of graphics applications is highly dependent on the rate at which frames are processed, it is important to devise a DVFS scheme that minimizes deadline misses due to inaccuracies in workload prediction. In this paper, we demonstrate that tiled-graphics renderers exhibit substantial advantages over immediate-mode renderers in obtaining access to frame parameters that help in enhancing the workload estimation accuracy. We also show that, operating at a finer granularity of “tiles” as opposed to “frames” allows early detection and corrective action in case of a mis-prediction. We propose an accurate workload estimation technique and two DVFS schemes: (i) tile-history based DVFS and (ii) tile-rank based DVFS for tiled-rendering architectures. The proposed schemes are demonstrated to be more efficient in terms of power and performance than the frame level DVFS schemes proposed in recent literature. With a system with 8 DVFS levels, our tile-history based DVFS scheme results in 60% improvement in quality (deadline misses) over the frame history based DVFS schemes and gives 58% saving in energy. The more sophisticated tile-rank based scheme achieves 75% improvement in quality over the frame history based DVFS scheme and results in 58% saving in energy. We have also compared the efficiency of the proposed tile-level DVFS schemes with frame-level schemes for different number of DVFS levels, and found that while the frame-level schemes suffer from increasing deadline misses as the frequency levels increase, the impact on tile-level schemes is negligible. The Energy per Frame-rate for our scheme is the minimum, indicating that it delivers the best performance-energy results.
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