A novel methodology for hierarchical test generation using functional constraint composition

The increasing functionality of processor designs has posed a severe challenge for generating high quality manufacturing tests, which can be applied at native speeds. A previous approach was to target one module at a time and extract functional constraints on the module under test (MUT) in order to reduce the complexity for test generation. However, when this technique is applied to large designs, the embedded modules themselves become too complex for an ATPG tool to handle. If sub-modules within these complex modules are considered, the extraction of constraints may prove to be too tedious. In this paper, a novel methodology to extract constraints hierarchically is presented. We use synthesis tools to eliminate redundant logic during the constraint extraction process. The proposed methodology also facilitates the reuse of constraints extracted for different sub-modules at a given level of hierarchy. This technique was applied to the ALU unit of the ARM Verilog benchmark design, and the results presented show that this technique makes the constraint extraction process more useful for large designs.