导电桥式随机存取存储器(CBRAM)中成形、SET和RESET操作的实验和理论理解

2014 IEEE International Electron Devices Meeting Pub Date : 2014-12-01 DOI:10.1109/IEDM.2014.7046997

J. Guy, G. Molas, P. Blaise, C. Carabasse, M. Bernard, A. Roule, G. Carval, Veronique Sousa, H. Grampeix, V. Delaye, A. Toffoli, J. Cluzel, P. Brianceau, O. Pollet, V. Balan, S. Barraud, O. Cueto, Gérard Ghibaudo, F. Clermidy, B. D. Salvo, L. Perniola

{"title":"导电桥式随机存取存储器(CBRAM)中成形、SET和RESET操作的实验和理论理解","authors":"J. Guy, G. Molas, P. Blaise, C. Carabasse, M. Bernard, A. Roule, G. Carval, Veronique Sousa, H. Grampeix, V. Delaye, A. Toffoli, J. Cluzel, P. Brianceau, O. Pollet, V. Balan, S. Barraud, O. Cueto, Gérard Ghibaudo, F. Clermidy, B. D. Salvo, L. Perniola","doi":"10.1109/IEDM.2014.7046997","DOIUrl":null,"url":null,"abstract":"In this paper, we deeply investigate for the 1st time at our knowledge the impact of the CBRAM memory stack on the Forming, SET and RESET operations. Kinetic Monte Carlo simulations, based on inputs from ab-initio calculations and taking into account ionic hopping and chemical reaction dynamics are used to analyse experimental results obtained on decananometric devices. We propose guidelines to optimize the CBRAM stack, targeting Forming voltage reduction, improved trade-off between SET speed and disturb immunity (time voltage dilemma) and window margin increase (RESET efficiency).","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"65 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"29","resultStr":"{\"title\":\"Experimental and theoretical understanding of Forming, SET and RESET operations in Conductive Bridge RAM (CBRAM) for memory stack optimization\",\"authors\":\"J. Guy, G. Molas, P. Blaise, C. Carabasse, M. Bernard, A. Roule, G. Carval, Veronique Sousa, H. Grampeix, V. Delaye, A. Toffoli, J. Cluzel, P. Brianceau, O. Pollet, V. Balan, S. Barraud, O. Cueto, Gérard Ghibaudo, F. Clermidy, B. D. Salvo, L. Perniola\",\"doi\":\"10.1109/IEDM.2014.7046997\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we deeply investigate for the 1st time at our knowledge the impact of the CBRAM memory stack on the Forming, SET and RESET operations. Kinetic Monte Carlo simulations, based on inputs from ab-initio calculations and taking into account ionic hopping and chemical reaction dynamics are used to analyse experimental results obtained on decananometric devices. We propose guidelines to optimize the CBRAM stack, targeting Forming voltage reduction, improved trade-off between SET speed and disturb immunity (time voltage dilemma) and window margin increase (RESET efficiency).\",\"PeriodicalId\":309325,\"journal\":{\"name\":\"2014 IEEE International Electron Devices Meeting\",\"volume\":\"65 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"29\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2014.7046997\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2014.7046997","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 29

摘要

在本文中，我们第一次深入研究了CBRAM内存堆栈对成形、SET和RESET操作的影响。动力学蒙特卡罗模拟，基于从从头算输入，并考虑到离子跳跃和化学反应动力学是用来分析实验结果得到的decananometric装置。我们提出了优化CBRAM堆栈的指导方针，目标是降低成形电压，改善SET速度和干扰抗扰度(时间电压困境)之间的权衡，以及增加窗口裕度(RESET效率)。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Experimental and theoretical understanding of Forming, SET and RESET operations in Conductive Bridge RAM (CBRAM) for memory stack optimization

In this paper, we deeply investigate for the 1st time at our knowledge the impact of the CBRAM memory stack on the Forming, SET and RESET operations. Kinetic Monte Carlo simulations, based on inputs from ab-initio calculations and taking into account ionic hopping and chemical reaction dynamics are used to analyse experimental results obtained on decananometric devices. We propose guidelines to optimize the CBRAM stack, targeting Forming voltage reduction, improved trade-off between SET speed and disturb immunity (time voltage dilemma) and window margin increase (RESET efficiency).

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2014 IEEE International Electron Devices Meeting

自引率

0.00%

发文量