CMOS电容耦合逻辑(C/sup 3/L)电路

Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI:10.1109/APASIC.2000.896901

Hong-Yi Huang, Teng-Neng Wang

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引用次数: 2

摘要

多值逻辑作为构建未来集成电路的一个有前途的候选方案，已经引起了相当大的关注。电容耦合技术是解决性能问题的有效方法之一。本文提出了电容耦合逻辑(C/sup 3/L)电路来实现CMOS逻辑门。使用该技术可以很容易地实现多输入NAND、NOR、AOI和OAI门。设计并验证了全加法器的进位和电路。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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CMOS capacitor coupling logic (C/sup 3/L) circuits

The multi-valued logic has been drawing considerable attention as a promising candidate for building future integrated circuits. The capacitor coupling technique is one of the effective methods to approach the performance issue. In this paper the capacitor coupling logic (C/sup 3/L) circuit to implement CMOS logic gates is proposed. The multiple inputs NAND, NOR, AOI, and OAI gates can be easily realized using the technique. Furthermore, the carry and sum circuit of a full-adder is designed and verified.

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Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)

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