A new DRAM cell structure with Capacitor-Equiplanar-to-Bitline (CEB) for bitline coupling noise elimination

A new cell structure for minimizing bit-line coupling noise in DRAM with stack capacitor is proposed in this paper. The node capacitors are fabricated in between bit-lines, so that the bit-line to bit-line capacitance coupling is blocked by the node capacitor and is shielded by the plate. This scheme is referred to as Capacitor-Equiplanar-to-Bitline (CEB). In this way, as 3D simulation shows, the bit-line coupling noise can be almost eliminated to <1% of total bit-line capacitance. The SPICE simulation shows /spl sim/3 ns faster bit-line signal sensing in 0.25 /spl mu/m 64 Mb CMOS DRAM. The CEB scheme also leads to a smaller topology and a simpler fabrication process.