基于可重构指令单元结构的低密度奇偶校验码实时可编程编码器的流水线实现

Zahid Khan, T. Arslan
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引用次数: 13

摘要

本文提出了一种基于IEEE P802.16E/D7标准的实时可编程不规则低密度奇偶校验(LDPC)编码器的流水线实现。编码器是可编程的帧大小从576到2304和五种不同的码率。H矩阵有效地生成和存储为特定的帧大小和码率。编码器是在可重构指令单元架构上实现的,该架构是最近出现的一种超低功耗、高性能、ANSI-C可编程嵌入式内核。应用不同的通用和特定于体系结构的优化技术来提高吞吐量。在这种架构下,吞吐量达到了10到19 Mbps。流水线/多核实现的最大吞吐量为78 Mbps
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Pipelined Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Architecture
This paper presents pipelined implementation of a real time programmable irregular low density parity check (LDPC) encoder as specified in the IEEE P802.16E/D7 standard. The encoder is programmable for frame sizes from 576 to 2304 and for five different code rates. H matrix is efficiently generated and stored for a particular frame size and code rate. The encoder is implemented on reconfigurable instruction cell architecture which has recently emerged as an ultra low power, high performance, ANSI-C programmable embedded core. Different general and architecture specific optimization techniques are applied to enhance the throughput. With the architecture, a throughput from 10 to 19 Mbps has been achieved. The maximum throughput achieved with pipelining/multi-core is 78 Mbps
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