一种轨对轨输入恒g/sub / CMOS运算跨导放大器的新架构

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 1900-01-01 DOI:10.1109/LPE.2003.1231913

M. M. Ahmadi, R. Lotfi, M. Sharif-Bakhtiar

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引用次数: 0

摘要

提出了一种恒g/sub -m /、轨对轨(R-R)输入级的新架构，在整个输入共模电压范围内g/sub -m /的偏差小于5%。在此基础上，提出了一种基于浮动电流源的折叠级联放大器结构。利用这些技术，在0.8 /spl mu/m CMOS技术中实现了具有100 MHz单位增益带宽、106 dB增益、60/spl度/相位裕度、2.65 V摆幅和6.4 nV//spl径向/Hz输入参考噪声、R-R输入共模范围的低功率跨导运算放大器(OTA)。这个放大器从3V电源耗散10mw。

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A new architecture for rail-to-rail input constant-g/sub m/ CMOS operational transconductance amplifiers

A new architecture for constant-g/sub m/, rail-to-rail(R-R) input stages is presented that has less than 5% deviation in g/sub m/ over the entire range of the input common-mode voltage. Furthermore, a new structure for folded cascode amplifier based on the use of a floating current source is presented. Employing these techniques a low-power operational transconductance amplifier (OTA) with 100 MHz unity-gain bandwidth, 106 dB gain, 60/spl deg/ phase margin, 2.65 V swing, and 6.4 nV//spl radic/Hz input-referred noise with R-R input common-mode range is realized in a 0.8 /spl mu/m CMOS technology. This amplifier dissipates 10 mW from a 3V power supply.

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Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.

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