一个8.2 pj /bit, 56gb /s的大反向终端行波调制器驱动

2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) Pub Date : 2021-12-05 DOI:10.1109/BCICTS50416.2021.9682462

Hector Andrade, Aaron Maharry, Luis A. Valenzuela, Navid Hosseinzadeh, C. Schow, J. Buckwalter

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引用次数: 4

摘要

本文提出了一种56 Gb/s行波Mach-Zehnder调制器(TW-MZM)驱动器，该驱动器采用级联码拓扑结构，采用GlobalFoundries 8XP 130纳米SiGe BiCMOS工艺制造。准开路集电极设计提供4.4 ${{\ mathm {V}}_{\text{pp}}}$差分摆幅，降低二次反射幅值，同时保持460 mW的低总功耗，即56 Gb/s时的8.2 pJ/bit(包括调制器终端电阻损耗)。驱动器有两个变体，每个变体都提供不同的TW-MZM偏置方案，以实现在两个不同的PN结移相器偏置下的操作。以高达60gb /s的速度呈现眼图以及误码率(BER)浴盆曲线。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An 8.2-pJ/bit, 56 Gb/s Traveling-wave Modulator Driver with Large Reverse Terminations

This paper presents a 56 Gb/s traveling-wave Mach-Zehnder Modulator (TW-MZM) driver fabricated in the GlobalFoundries 8XP 130-nm SiGe BiCMOS process employing a cascode topology. The quasi-open collector design delivers a 4.4 ${{\mathrm{V}}_{\text{pp}}}$ differential swing and reduces the amplitude of the secondary reflections while maintaining a low overall power consumption of 460 mW, or 8.2 pJ/bit at 56 Gb/s, including the modulator termination resistance dissipation. The driver has two variants, each of which provides a different TW-MZM biasing scheme, to enable operation at two different PN junction phase shifter biases. Eye-diagrams at up to 60 Gb/s are presented as well as bit-error rate (BER) bathtub curves.

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来源期刊

2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)

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