10nm节点代DRAM器件的间歇单比特故障分析

H. Seo, T. Rim, Eunsun Lee, Sekyoung Jang, Kyosuk Chae, Jeonghoon Oh, H. Ban, Jooyoung Lee
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引用次数: 0

摘要

间歇性单比特(SB)故障是DRAM技术发展中最重要的问题之一,因为它几乎无法再现和屏蔽。本文从理论上分析了间歇式SB故障。在物理建模的基础上,提出了几种降低间歇SB故障率的技术方法,并得到了降低间歇SB故障率的实验结果。在此基础上,对系统的故障率进行了预测。SB失败率在预测和结果之间的一致性超过85%。因此,我们证明了我们的故障模型是适合于预测间歇性SB故障的发生。此外,我们可以从开发之初就提出设计下一代DRAM技术,以达到与上一代相同或更好的间歇性SB质量。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Analysis of Intermittent Single-bit Failure on 10-nm node generation DRAM Devices
The intermittent single-bit (SB) failure is one of the most important problems in DRAM technology development because it is almost impossible to reproduce and screen out. In this paper, the intermittent SB failure was analyzed theoretically. Based on our physical modeling, we suggested several technical methods to reduce the intermittent SB failure and got the experimental results that decrease the intermittent SB failure rate. Furthermore, we predicted the failure rate based on our theoretical model. The SB failure rate had over 85% consistency between prediction and results. Therefore, we proved that our failure modeling is appropriate for predicting the occurrence of the intermittent SB failure. Furthermore, we can propose the design of the next generation DRAM technology to achieve equivalent or better intermittent SB quality than the previous generation from the beginning of the development.
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