采用存根匹配拓扑的级联CE和CB输出功率级的16dbm d波段功率放大器

2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS) Pub Date : 2019-11-01 DOI:10.1109/BCICTS45179.2019.8972772

Badou Sene, H. Knapp, Hao Li, Jonas Kammerer, S. Majied, K. Aufinger, J. Fritzin, Daniel Reiter, N. Pohl

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引用次数: 2

摘要

本文提出了一种采用130 nm SiGe BiCMOS技术设计的具有交流耦合共发射极和共基极级的功率放大器(PA)。放大器工作在d波段，由两个驱动级和一个输出功率级组成。在143 GHz时，信号增益为39.8 dB，最大饱和输出功率(PSAT)为16 dBm。PAE峰值为5.4%，而芯片从3.3 V电源中吸取220 mA。包括衬垫在内，芯片的占地面积为0.66 mm2。据作者所知，这是使用硅基技术在该频率范围内报告的PSAT的最高值。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 16-dBm D-Band Power Amplifier with a Cascaded CE and CB Output Power Stage Using a Stub Matching Topology

This work presents the design of a power amplifier (PA) with an AC-coupled common-emitter and common-base stage in a 130 nm SiGe BiCMOS technology. The amplifier operates in the D-band and consists of two driving stages followed by an output power stage. At 143 GHz a small signal gain of 39.8 dB and a maximum saturated output power (PSAT) of 16 dBm is achieved. The PAE peak value is 5.4 %, while the chip draws 220 mA from a 3.3 V power supply. Including pads the chip consumes an area of 0.66 mm2. To the best of the authors’ knowledge this is the highest value for PSAT reported in this frequency range using silicon-based technologies.

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2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)

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