用于低端射频产品的晶圆级芯片级封装

Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004. Pub Date : 2004-09-08 DOI:10.1109/SMIC.2004.1398162

M. Bartek, G. Zilber, D. Teomin, A. Polyakov, S. Sinaga, P. Mendes, J. Burghartz

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引用次数: 4

摘要

本文简要介绍了晶圆级芯片级封装技术，并分析了其在射频集成电路封装中的附加价值。特别是，通过衬底减薄和沟槽以及射频无源(电感器，天线)的嵌入来抑制衬底串扰的可能性。壳型晶圆级封装解决方案被用作研究案例，介绍其制造方面及其在射频集成电路封装方面的潜力。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Wafer-level chip-scale packaging for low-end RF products

The paper gives a short overview of wafer-level chip-scale packaging technology and analyses its added value in the packaging of RF ICs. Particularly, the possibilities of substrate crosstalk suppression by substrate thinning and trenching together with embedding of RF passives (inductors, antennas) are addressed. The Shellcase-type wafer-level packaging solution is used as a study case presenting its fabrication aspects and its potential for RF IC packaging.

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来源期刊

Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.

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