C. Maneux, C. Mukherjee, M. Deng, Bruno N. Wesling, Lucas Réveil, Z. Stanojević, O. Baumgartner, G. Larrieu, I. O’Connor, A. Poittevin
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Circuit Design Flow dedicated to 3D vertical nanowire FET
To continue transistor downscaling beyond lateral 7nm devices, gate-all-around (GAA) junction-less vertical nanowire field effect transistors (VNWFET) represent a promising option. This invited paper presents the circuit design flow based on a vertical junctionless transistor technology. On the basis of state-of-the-art junctionless nanowire transistors (JLNT), DC characterization, compact modelling, EM simulation and parameter extraction are described in details. Using this circuit design flow, a set of innovative 3D circuit architectures are explored.
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