{"title":"使用硬件描述语言进行建模和仿真","authors":"J. Armstrong","doi":"10.1109/ASIC.1997.617031","DOIUrl":null,"url":null,"abstract":"The role of HDL modeling and simulation in the design process is discussed. The modeling process involves both model and model test development. Simulation is used to ensure model correctness. Being able to create HDL models of complex systems is imperative in designing today's systems, but model creation and validation is itself a complex task. Intelligent use of tools is necessary to simplify of this effort. Hardware description languages such as VHDL have a powerful set of constructs, but the modeler must keep in mind the model's application when coding it. Model test benches that can be reused throughout the design cycle and simulation efficiency are critical to effective model testing.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Modeling and simulation with hardware description languages\",\"authors\":\"J. Armstrong\",\"doi\":\"10.1109/ASIC.1997.617031\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The role of HDL modeling and simulation in the design process is discussed. The modeling process involves both model and model test development. Simulation is used to ensure model correctness. Being able to create HDL models of complex systems is imperative in designing today's systems, but model creation and validation is itself a complex task. Intelligent use of tools is necessary to simplify of this effort. Hardware description languages such as VHDL have a powerful set of constructs, but the modeler must keep in mind the model's application when coding it. Model test benches that can be reused throughout the design cycle and simulation efficiency are critical to effective model testing.\",\"PeriodicalId\":300310,\"journal\":{\"name\":\"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-09-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1997.617031\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1997.617031","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Modeling and simulation with hardware description languages
The role of HDL modeling and simulation in the design process is discussed. The modeling process involves both model and model test development. Simulation is used to ensure model correctness. Being able to create HDL models of complex systems is imperative in designing today's systems, but model creation and validation is itself a complex task. Intelligent use of tools is necessary to simplify of this effort. Hardware description languages such as VHDL have a powerful set of constructs, but the modeler must keep in mind the model's application when coding it. Model test benches that can be reused throughout the design cycle and simulation efficiency are critical to effective model testing.