采用动态放大器和动态SAR量化器的二阶Delta Sigma模数调制器

2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) Pub Date : 2016-10-01 DOI:10.1109/ISPACS.2016.7824725

Chunhui Pan, H. San, Tsugumichi Shibata

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引用次数: 8

摘要

采用90nm CMOS技术设计和制造了一款采用动态模拟元件的Delta Sigma AD调制器。实验样机的测量结果证明了所提出的开关电容(SC)结构实现基于环形放大器的积分器和基于动态比较器的逐次逼近寄存器(SAR)量化器的二阶Delta Sigma AD调制器的可行性。调制器中的积分器采用无静电流环形放大器实现。前馈调制器中的多位量化器和模拟加法器是由电容阵列和动态比较器组成的嵌入式SAR模数转换器(ADC)实现的。当不使用前置放大器时，动态比较器不会耗散静态功率。在带宽为BW=94kHz的情况下，以12MS/s的速度采样正弦波- 1dBFS输入，获得峰值SNDR=77.51dB和SNR=80.08dB的测量结果。当电源电压为1.1V时，调制器的模拟总功耗为0.37mW。

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A 2nd-order Delta Sigma AD modulator using dynamic amplifier and dynamic SAR quantizer

A proof-of-concept Delta Sigma AD modulator using dynamic analog components is designed and fabricated in 90nm CMOS technology. The measurement results of an experimental prototype demonstrate the feasibility of the proposed switched-capacitor (SC) architecture to realize a 2nd-order Delta Sigma AD modulator with ring amplifier based integrators and dynamic comparator based successive approximation register (SAR) quantizer. The integrators in the modulator are realized by ring amplifier without static current. Multi-bit quantizer and analog adder in the feedforward modulator is realized by a passive-adder embedded SAR analog-to-digital converter (ADC) which consists of capacitor array and a dynamic comparator. The dynamic comparator does not dissipate static power when a pre-amplifier is not used. Measurement results of peak SNDR=77.51dB and SNR=80.08dB are achieved while a sinusoid −1dBFS input is sampled at 12MS/s for the bandwidth is BW=94kHz. The total analog power consumption of the modulator is 0.37mW while the supply voltage is 1.1V.

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2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)

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