传真阴影校正器

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1984.1156566

M. Togashi, S. Sato, S. Ohshima, K. Aruga, T. Nakamura

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引用次数: 4

摘要

本文将介绍一个5.7mm × 5.73mm的芯片，采用3μm CMOS技术，拥有9000个晶体管，功耗为200mW。该处理器集成了片上6b并行ADC，在1MHz转换速率下实现了3%的校正精度。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Facsimile shading corrector

This paper will cover a 5.7mm × 5.73mm chip with 9000 transistors using 3μm CMOS technology and a dissipation of 200mW. The processor incorporates an on-chip 6b parallel ADC and achieves 3% correction accuracy at a 1MHz conversion rate.

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来源期刊

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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