Uitra-low on-resistance p-channel lateral DMOS fabricated on [110]-oriented Si substrate

This paper presents a p-channel lateral DMOS (LDMOS) featuring improved onresistance through the use of a (1 10)-oriented Si substrate. The specific on-resistance of this LDMOS is believed to be the lowest among p-channel power MOSFETs reported to date. P-channel power MOSFETs are still widely used in such applications as high-side switching and complementary circuits even though their on-resistance, Ron, is about three times higher than that of n-channel devices having the same chip-size. While there is a need to reduce the Ron value of these devices, conventional (100)-substrates do not have a suitable orientation for this purpose because their hole mobility is lower than that of (1 10)-substrates. In this study, we fabricated p-channel LDMOS on both (100)and (1 10)-substrates and compared their on-resistance. Both types of samples were fabricated using double metallization and a hexagonal pattern similar to that described in ref. 1. The resistivity of the n-type substrates used in fabricating both sample types was kept constant at