III-V型半导体纳米线的电荷约束机制

O. Marquardt, P. Corfdir, J. Lähnemann, M. Ramsteiner, O. Brandt, L. Geelhaar, M. Hill, L. Lauhon, A. Hassan, U. Pietsch
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引用次数: 0

摘要

III-V型半导体纳米线在新型光电器件中具有独特的应用前景。由于它们的大表面体积比,实现超越平面生长能力的异质结构,仍然可以集成在硅基电子产品中,成为可能。此外,在砷化镓纳米线中观察到多型性,即不同的晶相共存于同一纳米线中。由于不同的晶相具有不同的电子特性,可以利用这一特性形成具有原子平面界面和非常小的弹性变形的晶相异质结构。我们将讨论这种纳米线的电子结构模拟的细节,并介绍最近的研究实例。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Charge confining mechanisms in III-V semiconductor nanowire
III-V semiconductor nanowires exhibit unique features for application in novel optoelectronic devices. Due to their large surface-to-volume ratio, the realization of heterostructures beyond the capabilities of planar growth, that can still be integrated in Si-based electronics, becomes possible. Furthermore, polytypism was observed e.g. in GaAs nanowires such that different crystal phases coexist in the same nanowire. As different crystal phases have different electronic properties, this feature can be exploited to form crystal-phase heterostructures with atomically flat interfaces and only very small elastic deformation. We will discuss the specifics of electronic-structure simulations in such nanowires and present recent example studies.
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