On the Ballistic Transport in Si Nano-Devices

The field of reliability physics for microelectronic devices is facing a significant challenge during the last decade due to the fact that the technology node (channel length and gate oxide size) has been reduced to the dimensions of charged carriers “mean free path” of silicon, which is about 15 nm at room temperature. This may involve the physical mechanism of ballistic conductance at the channel and at the gate of a MOSFET device. Recently, reliability research programs have made significant progress and developed new theoretical models and experimental methods that would fit the down scaling trend and explain the wearout mechanisms with regards to an innovative reliability physics approach. The classical, reliability common model, High Temperature Operational Life (HTOL) was found to be limited in its ability to distinguish between the dominating failure mechanisms (HCI, BTI, TDDB, EM) and the reliability physics standard methods, that are assessing the lifetime of a specific structure for just one particular mechanism at a time. More recently, a new model, named Multi Failure Mechanism, MTOL, has been introduced and posed a better understanding of the dominating failure mechanisms under various stressed conditions. Experiments were carried out on advanced technologies FPGA devices of Xilinx 45 and 28 nanometer. The insitu monitored experimental data enabled to calculate the activation energy of various degradation mechanisms, providing a more accurate and realistic prediction of the lifetime and point out on the apparent dominating wearout mechanisms. In this paper we report, for the first time, on a new phenomenon that was observed on 28 nm FPGA devices during their reliability testing. We employed the MTOL model at a temperature range of −60°C up to 160°C. The experimental results for 28 nm were compared to the 45 nm data (reported recently by Bernstein et al.) that have been recorded under identical testing conditions. From the comparison of the normalized degradation rate versus temperature, a clear deviation could be noted; the 28 nm devices have shown a distinct transition of the dominating failure mechanism at a particular temperature, whereas the 45 nm devices have not shown any transition along the entire temperature range of the test. Furthermore, the calculated values could be correlated to the recent published data, attributing the transistor channel conductance to the effect of “short channel ballistic conductance” at a lower temperature range. At higher temperatures (higher than the transition temperature), both 45 and 28 nm devices have shown similar slopes (normalized ring oscillator frequency versus temperature). To the best of our knowledge, such temperature dependence has not been reported up to now. $T$ his may indicate on a pronounced advantage of the lower node devices (28 nm) for operation at lower temperatures. Nevertheless, our study is ongoing to lower technology nodes (20 nm and 16 nm), which may provide additional data that will support this new hypothesis.