Performance investigation of charge plasma based dual material gate junctionless transistor

In this paper, the design aspects of charge plasma based junctionless transistors viz., (1) doping-less dual material double gate (DL-DMDG) junctionless transistor and (2) Gate stacked architecture of DL-DMDG JLT are used to evaluate the device performances. The n+ source/drain regions are formed by employing charge plasma technique over the intrinsic silicon. Dual material gate architecture helps to minimize the delay and gate stacked architecture helps to have better control over channel region. The performances metrics such as, subthreshold slope (SS), fluctuation in threshold voltage (VT), drain induced barrier lowering (DIBL), intrinsic delay and energy delay product are analysed for different silicon film thickness (Tsi), gate length (LG), and gate work-functions difference (δW). The comparative analysis has been done with conventional heavily doped dual material double gate (DMDG) JLT and its gate stacked architecture (GSDMDG) of JLT. The SS, VT, intrinsic delay and energy delay product of DL-DMDG and DL-GSDMDG JLTs are less sensitive to the variations in aforementioned device parameters as compared to conventional doped DMDG and GSDMDG JLTs. Moreover, DL-GSDMDG JLT shows remarkable improvement over other mentioned device configurations.