500MHz-BW−52.5dB-THD电压-时间转换器，采用两步过渡逆变器

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference Pub Date : 2016-09-01 DOI:10.1109/ESSCIRC.2016.7598262

Takuji Miki, N. Miura, Kento Mizuta, S. Dosho, M. Nagata

{"title":"500MHz-BW−52.5dB-THD电压-时间转换器，采用两步过渡逆变器","authors":"Takuji Miki, N. Miura, Kento Mizuta, S. Dosho, M. Nagata","doi":"10.1109/ESSCIRC.2016.7598262","DOIUrl":null,"url":null,"abstract":"This paper presents a 500MHz-BW -52.5dB-THD Voltage-to-Time Converter (VTC) in 28nm CMOS. A two-step transition inverter raises the VT conversion gain to 100ps/V which is >10× higher than a conventional current-starved inverter. The number of required inverter stages is reduced to 4 from 64, resulting in 1/8 conversion latency and thus 13.2dB THD suppression at 500MHz full Nyquist. A test-chip measurement successfully demonstrates -52.5dB THD at 500MHz without sampling-and-hold. Effective VT conversion linearity is measured to be 1ps/LSB with INL/DNL of less than +/-0.53LSB. The proposed VTC consumes 84μm2 silicon area and 0.18mW at 1GS/s.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A 500MHz-BW −52.5dB-THD Voltage-to-Time Converter utilizing a two-step transition inverter\",\"authors\":\"Takuji Miki, N. Miura, Kento Mizuta, S. Dosho, M. Nagata\",\"doi\":\"10.1109/ESSCIRC.2016.7598262\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a 500MHz-BW -52.5dB-THD Voltage-to-Time Converter (VTC) in 28nm CMOS. A two-step transition inverter raises the VT conversion gain to 100ps/V which is >10× higher than a conventional current-starved inverter. The number of required inverter stages is reduced to 4 from 64, resulting in 1/8 conversion latency and thus 13.2dB THD suppression at 500MHz full Nyquist. A test-chip measurement successfully demonstrates -52.5dB THD at 500MHz without sampling-and-hold. Effective VT conversion linearity is measured to be 1ps/LSB with INL/DNL of less than +/-0.53LSB. The proposed VTC consumes 84μm2 silicon area and 0.18mW at 1GS/s.\",\"PeriodicalId\":246471,\"journal\":{\"name\":\"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference\",\"volume\":\"32 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2016.7598262\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2016.7598262","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 7

摘要

本文提出了一种500MHz-BW -52.5dB-THD电压-时间转换器(VTC)。两步过渡逆变器将VT转换增益提高到100ps/V，比传统的电流匮乏逆变器高>10倍。所需的逆变器级数从64个减少到4个，导致1/8转换延迟，因此在500MHz全奈奎斯特时抑制13.2dB THD。测试芯片测量成功地演示了-52.5dB THD在500MHz下没有采样和保持。测量到有效VT转换线性度为1ps/LSB, INL/DNL小于+/-0.53LSB。所提出的VTC在1GS/s下消耗84μm2硅面积和0.18mW。

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A 500MHz-BW −52.5dB-THD Voltage-to-Time Converter utilizing a two-step transition inverter

This paper presents a 500MHz-BW -52.5dB-THD Voltage-to-Time Converter (VTC) in 28nm CMOS. A two-step transition inverter raises the VT conversion gain to 100ps/V which is >10× higher than a conventional current-starved inverter. The number of required inverter stages is reduced to 4 from 64, resulting in 1/8 conversion latency and thus 13.2dB THD suppression at 500MHz full Nyquist. A test-chip measurement successfully demonstrates -52.5dB THD at 500MHz without sampling-and-hold. Effective VT conversion linearity is measured to be 1ps/LSB with INL/DNL of less than +/-0.53LSB. The proposed VTC consumes 84μm2 silicon area and 0.18mW at 1GS/s.

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ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference

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