J. Selleck, R. Kenyon, D. Gaffney, F. Wiedman, A. Bhattacharyya, P. Mollier
{"title":"64K动态1/N分数器件双极存储器","authors":"J. Selleck, R. Kenyon, D. Gaffney, F. Wiedman, A. Bhattacharyya, P. Mollier","doi":"10.1109/ISSCC.1980.1156079","DOIUrl":null,"url":null,"abstract":"This report will cover a 1/N fractional device bipolar memory cell - the FET one-device memory cell equivalent - noting that by reversing the orientation of the transistor and capacitor, the density, thin dielectric and polysilicon techniques of FET technology can be combined with the speed of bipolar technology,","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"244 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"64K dynamic 1/N fractional device bipolar memory\",\"authors\":\"J. Selleck, R. Kenyon, D. Gaffney, F. Wiedman, A. Bhattacharyya, P. Mollier\",\"doi\":\"10.1109/ISSCC.1980.1156079\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This report will cover a 1/N fractional device bipolar memory cell - the FET one-device memory cell equivalent - noting that by reversing the orientation of the transistor and capacitor, the density, thin dielectric and polysilicon techniques of FET technology can be combined with the speed of bipolar technology,\",\"PeriodicalId\":229101,\"journal\":{\"name\":\"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"244 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1980.1156079\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1980.1156079","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This report will cover a 1/N fractional device bipolar memory cell - the FET one-device memory cell equivalent - noting that by reversing the orientation of the transistor and capacitor, the density, thin dielectric and polysilicon techniques of FET technology can be combined with the speed of bipolar technology,