On-line detection of faults in carry-select adders

Paper 35.3 91 2 from the previous stage. If the actual carry-in is ‘0’ then the sum multiplexed from the first unit is selected, alternatively if the carry-in is. ‘ 1 ’ then the sum from the second unit is selected. A carry select adder of arbitrary size can be deigned by cascading together an appropriate number of such 4-bit adders. This paper concentrates on designing a scheme for implementing self-checking carry-select adders. Several techniques have been proposed in recent years for designing self-checking adders [2][3][4]. Coding techniques such as Berger code, Residue code and arithmetic codes have been proposed for checking the hnctionality of the arithmetic units. a3 b3 a2 b2 al b l QO bO