A New DC-Offset and I/Q-Mismatch Compensation Technique for a CMOS Direct-Conversion WLAN Transmitter

This paper presents a novel DC-offset and I/Q-mismatch compensation technique with short convergence time, high accuracy, and low-circuit-complexity. In this technique, all kinds of transmitter nonidealities, i.e. an offset and a mismatch, can be detected using adequate pair of DC test signals. The test signals are designed so that the envelope of the modulator RF outputs for each test signal fluctuates when the offset or mismatch exists. The fluctuations are converted to a baseband signal using an envelope detector which is designed as a signal dynamic range compressor to avoid saturation in following stages. The polarity of this fluctuation is detected by a comparator instead of a multi-bit analog to digital converter, and a binary-search-type algorithm optimizes parameters for the offset and mismatch compensation using the 1-bit comparator output. This technique was demonstrated in a 0.18-mum CMOS 5-GHz-band WLAN transmitter. The DC offset was suppressed to -43 dBc and the image tone was suppressed to -49 dBc.