A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x 9-chip x 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization Problems

Combinatorial optimization problems, which are categorized into NP-hard problems, are emerging in ever-growing social systems, such as logistics, traffic, and so on. A new computer architecture, called an annealing processor (AP) [1–4], has advanced to solve such difficult problems efficiently as an accelerator in the computing systems. A specific type of AP discovers the ground state (optimal combination of variables, spins) of an Ising model in a short time by highly parallelizing the spin state update process based on simulated annealing (SA) [2–4]. We have built boards with nine AP chips connected to each other [5]. To lunch the annealing systems for real usage, it is necessary to provide a larger-scale annealing system. We built a multiple-board annealing system (AS) with a simple multi-board control beyond the multi-chip AS for the increasing amount of data in the real-world optimization problems. In order to realize such system, it is necessary to adopt a method in which the host board connected to the PC controls the other slave boards, rather than controlling each board individually. Our CMOS-AS consists of three technologies: (i) a routing table to control communication between boards, (ii) a technology to synchronize the annealing process on each chip, and (iii) a compression technology for efficient propagation of spin information in inter-board communication where data transmission amount is limited. The CMOS-AS demonstrated noise reduction as an example of combinatorial optimization problems and multi-board operation of the 9x9x16k spin system with an annealing speed at least three orders of magnitude faster and higher accuracy than running the SG3 and SA on a CPU, conventional technologies to solve optimization problems.