集成电路布置图合成布线阶段的良率提高

A. Tyagi, M. Bayoumi, P. Manthravadi
{"title":"集成电路布置图合成布线阶段的良率提高","authors":"A. Tyagi, M. Bayoumi, P. Manthravadi","doi":"10.1109/ICWSI.1994.291264","DOIUrl":null,"url":null,"abstract":"An algorithm for integrated circuit yield enhancement in the routing phase of layout synthesis is proposed. The focus is on detailed routing. The proposed algorithm reduces layout critical area for short circuits. Critical area reduction is achieved without any penalties on net length. The defect tolerant features of the algorithm include efficient net merging and final track assignment aimed toward critical area reduction. The proposed algorithm overcomes the limitations associated with the existing defect tolerant routing algorithms.<<ETX>>","PeriodicalId":183733,"journal":{"name":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Yield enhancement in the routing phase of integrated circuit layout synthesis\",\"authors\":\"A. Tyagi, M. Bayoumi, P. Manthravadi\",\"doi\":\"10.1109/ICWSI.1994.291264\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An algorithm for integrated circuit yield enhancement in the routing phase of layout synthesis is proposed. The focus is on detailed routing. The proposed algorithm reduces layout critical area for short circuits. Critical area reduction is achieved without any penalties on net length. The defect tolerant features of the algorithm include efficient net merging and final track assignment aimed toward critical area reduction. The proposed algorithm overcomes the limitations associated with the existing defect tolerant routing algorithms.<<ETX>>\",\"PeriodicalId\":183733,\"journal\":{\"name\":\"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-01-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICWSI.1994.291264\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICWSI.1994.291264","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

摘要

提出了一种在版图综合布线阶段提高集成电路成品率的算法。重点是详细的路由。该算法减小了短路时的布局临界面积。在不影响净长度的情况下实现临界面积缩减。该算法的容错特性包括有效的网络合并和最终的航迹分配,以减少关键区域。该算法克服了现有容错路由算法的局限性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Yield enhancement in the routing phase of integrated circuit layout synthesis
An algorithm for integrated circuit yield enhancement in the routing phase of layout synthesis is proposed. The focus is on detailed routing. The proposed algorithm reduces layout critical area for short circuits. Critical area reduction is achieved without any penalties on net length. The defect tolerant features of the algorithm include efficient net merging and final track assignment aimed toward critical area reduction. The proposed algorithm overcomes the limitations associated with the existing defect tolerant routing algorithms.<>
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