基于fpga的维特比解码器的设计与实现

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-07 DOI:10.1109/ICVD.1999.745223

B. Pandita, S. Roy

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引用次数: 26

摘要

本文介绍了利用fpga实现维特比解码器的设计。在本文中，我们探索了一种基于FPGA的快速原型设计实现方法。我们使用高级合成来实现这一点。讨论了与Viterbi解码器相关的一些实现问题，如路径存储器的组织、决策存储器读取技术和时钟机制。

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Design and implementation of a Viterbi decoder using FPGAs

This paper describes the design at implementation of Viterbi decoder using FPGAs. In this paper we explore an FPGA based implementation methodology for rapidly prototyping designs. We use high level synthesis to achieve this. Some of the implementation issues related to the Viterbi decoder such as organization of path memory, decision memory reading techniques, and the clocking mechanism have been discussed.

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Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)

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