CMOS current-mode geometric-mean circuit with n inputs

A CMOS current-mode geometric-mean circuit composed of n compact logarithm circuits and one compact exponential circuit is proposed. Approaches for constructing the logarithm circuits and the exponential circuit are based on second-order Taylor series approximations. By gathering the n logarithm results and passing through the exponential circuit, we can obtain the geometric-mean results. The circuitry complexity is low with only (3n + 3) transistors. The simulation results indicate that the relative errors of the proposed circuit are less than 2:5% for input range from 40µA to 75µA for n ≤ 5.