在FPGA上实现MIMO-SDM-PNC中继站的有效设计方法

Minh Le Nguyen, X. Tran, Vu-Duc Ngo, Duc-Thang Nguyen, Tien Anh Vu, Quang-Kien Trinh
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引用次数: 0

摘要

本文提出了一种利用物理层网络编码(PNC)实现双向中继MIMO空分复用(MIMO- sdm)系统中继节点信号处理单元的有效设计方法,简称MIMO- sdm -PNC。所提出的MIMO-SDM-PNC中继节点的结构基于经过验证的低复杂度算法,该算法在FPGA实现的微架构级别进行了严格优化。使用Vivado 2019.2对最终的数字实现MIMO-SDM-PNC进行了评估。实现结果表明,以4 × 4 MIMO系统为例,该中继节点在典型商用FPGA器件上以合理的硬件成本实现了高达7 Gbps的准ml误码率性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An Effective Design Approach to Implementation of MIMO-SDM-PNC Relay Stations on FPGA
This paper presents an effective design approach to implementing the signal processing unit in the relay node in a two-way relay MIMO spatial division multiplexing (MIMO-SDM) system using physical-layer network coding (PNC), referred to as MIMO-SDM-PNC. The structure of the proposed MIMO-SDM-PNC relay node is based on a proven low-complexity algorithm that is rigorously optimized at a micro-architectural level for FPGA implementation. The final digital implemented MIMO-SDM-PNC has been evaluated using Vivado 2019.2. The implementation results show that in a case study of a 4 × 4 MIMO system, the relay node achieves up to 7 Gbps, quasi-ML BER performance with reasonable hardware cost on typical commercial FPGA devices.
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